System Verilog parameterise class with interface

Question

A protocol may be implemented over different physical layers, e.g.

interface async_if;
    logic tx;

    task send(int n);
        tx <= 0; // stop bit
        #10;
        // etc.
    endtask
endinterface

interface clkd_if;
    logic data;
    logic clk;

    task send(int n);
        foreach(n[ii]) begin
            data <= n[ii];
            clk <= 1;
            #10 clk <= 0;
            #10 ;
        end endtask
endinterface

Is there a way of parameterising a System Verilog class with an interface? The following doesn't seem to compile, because System Verilog doesn't regard interfaces as types.

class sender#(type I);
    virtual I if;
    function void send(int n);
        if.send(n);
    endfunction
endclass

Strangely enough, an interface is not a type, but a virtual interface is. — dave_59, Sep 16 '19 at 18:21

score 2 · Answer 1 · answered Sep 16 '19 at 13:44

You can parameterise a class with an interface in SystemVerilog. You just weren't doing it quite right. This works:

  class sender #(type I);
    I vif;  // 'if' is a reserved word and you don't want the 'virtual' here
    function void send(int n);
        vif.send(n);
    endfunction     
  endclass

Then you can:

  sender#(virtual async_if) s = new;

https://www.edaplayground.com/home

module M;

  interface async_if;
    logic tx;

    task send(int n);
        tx <= 0; // stop bit
        #10;
        // etc.
    endtask
  endinterface

  interface clkd_if;
    logic data;
    logic clk;

    task send(int n);
        foreach(n[ii]) begin
            data <= n[ii];
            clk <= 1;
            #10 clk <= 0;
            #10 ;
        end
    endtask
  endinterface

  class sender #(type I);
    I vif;
    function void send(int n);
        vif.send(n);
    endfunction     
  endclass

  sender#(virtual async_if) s = new;

endmodule

@user234461 What do you want to do that the above solution isn't solving? — Matthew Taylor, Sep 18 '19 at 12:09

score 0 · Answer 2 · answered Sep 18 '19 at 17:47

No, because as you said, it does not a data type (see the SystemVerilog LRM section A.2.2.1 for what is considered a data type).

Not sure what your use case is, but it looks very much like polymorphic interfaces is what you want. It involves embedding a class inside the interface that implements methods of a base virtual class.

System Verilog parameterise class with interface

2 Answers2