This question asks the general question. I'm asking about VHDL in particular, since the tools that question's answer mentions are for Java and PL/SQL. It doesn't need to be perfect, some manual interpretation would be fine. I'm doing this for an automated commit task.
EDIT 3/9/11: @phillipe pointed out automated commit task is inconsistent with manual interpretation. I'm trying to encourage other engineers to get rid of code and see that they did it. I guess a pessimistic tool would be better for commits; if it misses some code that isn't the end of the world. Or I could make it report the number of such lines and email me rather than stop the commit.