I have to solve this problem for my university course:
write in VHDL a circuit which, based on the control signal C, dives the operations shown in the table and also stores the result in a register sensitive to the falling edge.
C='0' OUT= A+B;C='1' OUT= A-B. Use only std_logic and std_logic_vector statements. A and B are 8-bit vectors.
Ok, I'll post my soluction and after I'll post my doubts.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
port( a,b,cin: in std_logic;
s,cout: out std_logic);
end fulladder;
architecture FA of fulladder is
signal p,g: std_logic;
begin
p<= a xor b;
g<= a and b;
s<= p xor cin;
cout<= g or (p and cin);
end FA;
entity ripplecarry8bit is
port(a,b:in std_logic_vector(7 downto 0);
cin: in std_logic;
cout: out std_logic;
s: out std_logic_vector(7 downto 0));
end ripplecarry8bit;
architecture RC8 of ripplecarry8bit is
signal c: std_logic_vector(6 downto 0);
component fulladder is
port(a,b,cin: in std_logic;
cout,s: out std_logic);
end component;
begin
fa0: fulladder port map(a(0),b(0),cin,c(0),s(0));
fa1: fulladder port map(a(1),b(1),c(0),c(1),s(1));
fa2: fulladder port map(a(2),b(2),c(1),c(2),s(2));
fa3: fulladder port map(a(3),b(3),c(2),c(3),s(3));
fa4: fulladder port map(a(4),b(4),c(3),c(4),s(4));
fa5: fulladder port map(a(5),b(5),c(4),c(5),s(5));
fa6: fulladder port map(a(6),b(6),c(5),c(6),s(6));
fa7: fulladder port map(a(7),b(7),c(6),cout,s(7));
end RC8;
entity ripplecarry9bit is
port(a,b:in std_logic_vector(8 downto 0);
cin: in std_logic;
cout: out std_logic;
s: out std_logic_vector(8 downto 0));
end ripplecarry9bit;
architecture RC9 of ripplecarry9bit is
signal c: std_logic_vector(7 downto 0);
component fulladder is
port(a,b,cin: in std_logic;
cout,s: out std_logic);
end component;
begin
fa0: fulladder port map(a(0),b(0),cin,c(0),s(0));
fa1: fulladder port map(a(1),b(1),c(0),c(1),s(1));
fa2: fulladder port map(a(2),b(2),c(1),c(2),s(2));
fa3: fulladder port map(a(3),b(3),c(2),c(3),s(3));
fa4: fulladder port map(a(4),b(4),c(3),c(4),s(4));
fa5: fulladder port map(a(5),b(5),c(4),c(5),s(5));
fa6: fulladder port map(a(6),b(6),c(5),c(6),s(6));
fa7: fulladder port map(a(7),b(7),c(6),c(7),s(7));
fa8: fulladder port map(a(8),b(8),c(7),cout,s(8));
end RC9;
entity complement is
port(a: in std_logic_vector(7 downto 0);
b: out std_logic_vector(8 downto 0));
end complement;
architecture COM of complement is
signal temp: std_logic_vector(7 downto 0);
component ripplecarry8bit is
port(a,b: std_logic_vector(7 downto 0);
cin: in bit;
cout: out bit;
s: out bit_vector(7 downto 0));
end component;
begin
temp<= not a;
rc: ripplecarry8bit port map(temp, "00000001", '0', b(8), b(7 downto 0));
end COM;
entity register is
port( d: in std_logic_vector(9 downto 0);
clk, clear: in std_logic;
q: out std_logic_vector(9 downto 0));
end register;
architecture R of register is
begin
process(clk, clear)
begin
if clear='1' then
q<="000000000";
elsif clock'event and clock='0' then
q<=d;
end if;
end process;
end R;
entity exam is
port( A,B: in std_logic_vector(7 downto 0);
clk, clear: in std_logic;
OUT: out std_logic_vector(9 downto 0));
end exam;
architecture E of exam is
signal compB, AA, BB: std_logic_vector(8 downto 0);
signal SUM, SUB, O: std_logic_vector(9 downto 0);
component complement is
port(a: in std_logic_vector(7 downto 0);
b: out std_logic_vector(8 downto 0));
end component;
component ripplecarry9bit is
port(a,b:in std_logic_vector(8 downto 0);
cin: in std_logic;
cout: out std_logic;
s: out std_logic_vector(8 downto 0));
end component;
component register is
port( d: in std_logic_vector(9 downto 0);
clk, clear: in std_logic;
q: out std_logic_vector(9 downto 0));
end component;
COM: complement port map(B, compB);
AA<= A(7) & A; --I'm extending A to 9-bit vector
BB<= B(7) & B; --I'm extending B to 9-bit vector
RCSUM: ripplecarry9bit port map (AA, BB, '0', SUM(9), SUM(8 downto 0));
RCSUB: ripplecarry9bit port map (AA, compB, '0', SUB(9),SUB(8 downto 0));
O<= SUM when C='1',
SUB when C='0';
R: register port map(O, clk, clear, OUT);
end E;
I'll explain my doubts.
1) I don't know if RCSUB: ripplecarry9bit port map (AA, compB, '0', SUB(9),SUB(8 downto 0)); is legit cause compA has the left bit as a sign and I don't know if for AA it's the same (it's not explicated in exercise structure).
2) 9-bit vector + 9-bit vector could give as output a 10-bit vector(I use this case as output) but could give as output a 9-bit vector, how can I manage this case in VHDL language?
