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I'm trying to solve some exercises, I have to shift a 8-bit vector named A into 2A (A+A).

my soluction for this is: (A(7) and '1') & A(6 downto 0) & '0';

after this I made a two's complement of A in this way:

entity complementare is
    port(a: in std_logic_vector(7 downto 0);
         b: out std_logic_vector(7 downto 0));
end complementare;

architecture C of complementare is
    signal mask, temp: std_logic_vector(7 downto 0);
    component ripplecarry8bit is
        port(a,b: std_logic_vector(7 downto 0);
             cin: in std_logic;
             cout: out std_logic;
             s: out std_logic_vector(7 downto 0));
    end component;
begin
    mask<="11111111";
    temp<=a nand mask;
    rc: ripplecarry8bit port map(temp, "00000001", '0', cout, b);
end C; 
--if you need I post ripplecarry code but consider it as a generic adder

To get -2A (-A-A) I was thinking to do this:

signal compA: std_logic_vector(7 downto 0);
compA: complementar port map(A, compA);

--shifting
(compA(7) and '1') & compA(6 downto 0) & '0'; -- -A

Now, my main doubt is about -A, after using complementar and after getting compA, I have to extend 8-bit vector into 9-bit vector (cause my output has to be 9-bit vector), I was thinking to do this but I have doubts:

'1' & compA; --or should I just append compA to a '0' value?
DarkPassenger
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    `A(7) and '1'` is equal to `A(7)`, you can just write `2A <= A & '0'` – grorel May 29 '18 at 11:39
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    `compA(7) and '1'` is the same as `compA(7)` so why not simple add a zero and be done. Left shift is the same logically as arithmetically. – Oldfart May 29 '18 at 11:40
  • `-2A = -A&'0'`. 1 to 2 bit example: `-1 = b'1'` ==> `-2 = b'10'`. – JHBonarius May 29 '18 at 13:29
  • ok thanks to all, but my main doubt is about -A, as I said in the last lines of the post! How can I extend 8-bit vector into 9-bit vector when it is negative. for istance, I want to extend `-A (8-bit)` into `-A (9-bit)`, I was thinking that I can't do `'0' & -A` cause the first bit must be `'1'` to rapresent a negative number! @JHBonarius @grorel @Oldfart – DarkPassenger May 29 '18 at 16:09
  • Sigh, let me try again: just add a zero to the RHS. Left shift is the same logically as arithmetically. If you do not understand that, read up on how two's complete numbers look like. – Oldfart May 29 '18 at 16:56
  • @Oldfart sorry man, I'll report an example: `"10011011"`, if I add a `'0'` to get my 9-bit vector, I'll have: `"010011011"` but this is strange cause a negative number must be have `'1'` as first bit, if I add `'0'` at the end the value will change. – DarkPassenger May 29 '18 at 17:11
  • That is not the right hand side, you are adding a zero to the left hand side. – Oldfart May 29 '18 at 17:53
  • @Oldfart as I wrote: if I add `'0'` at the end the value will change. – DarkPassenger May 29 '18 at 17:57
  • what is the MSB for a signed two's value? the sign bit. So copy the sign to the n'th bit. 1-to-2 bit: `b'1' = -1` => `b'11' = -1`. 2-to-3 bit: `b'10' = -2` => `b'110' = -2`. – JHBonarius May 29 '18 at 18:26
  • @JHBonarius ok so `'1' & compA` will be good to get `-A` and `compA & '0'` to get `-2A`! thanks a lot, and sorry for my misunderstandings – DarkPassenger May 29 '18 at 18:34
  • Uhm, no. that's totally not what I said. Please read up on signed arithmetic. – JHBonarius May 29 '18 at 18:35
  • man I said a lot of times that I have to use only `std_logic` and `std_logic_vector` statements – DarkPassenger May 30 '18 at 06:50
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    I don't think that JHBonarius was talking about the `signed` VHDL signal type, but to read about "signed arithmetic" in the mathematical way, i-e how do you code a negative value using 0 and 1 ? – grorel May 30 '18 at 09:13

1 Answers1

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Simple signed arithmetics solutions for your problem :

For a signal A which is an std_logic_vector of a size C_SIZEOF_A

signal A : std_logic_vector(C_SIZEOF_A-1 downto 0);

To get a signal equal to -A (same size):

Complement the signal value and add one to this result:

signal minus_A : std_logic_vector(C_SIZEOF_A-1 downto 0);

minus_A <= (not A) + 1; -- Warning here !!!

Warning: The '+' operator is not defined for std_logic_vector. You do the addition with the solution you prefer. I intentionaly don't want to give a solution here because the simplest one is to use signed signals but you said you can't.

To multiply a signal by 2 (signed or unsigned)

Add a null bit as LSB:

signal 2A : std_logic_vector(C_SIZEOF_A downto 0);

2A <= A & '0';

To extend a signal for 1 bit (signed) :

The MSB is the sign bit. Extend only this bit:

signal A_extended : std_logic_vector(C_SIZEOF_A downto 0);

A_extended <= A(C_SIZEOF_A-1) & A;

To extend a signal for 1 bit (unsigned) :

No sign bit here, simply add a '0':

signal A_extended : std_logic_vector(C_SIZEOF_A downto 0);

A_extended <= '0' & A;
grorel
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