How to give the output of one module to be used as an input by another module in verilog?

Question

//code for alu
module alu(result,A,B,control);
output reg [0:31] result;
input [0:31] A;
input [0:31]B;
input [0:5]control;
always @(*)
begin
case(control)
//F0 f1 ena enb inva inc fun
6'b011000:result=A;
6'b010100:result=B;
6'b011010:result=~A;
6'b101100:result=~B;
6'b111100:result=A+B;
6'b111101:result=A+B+1;
6'b111001:result=A+1;
6'b110101:result=B+1;
6'b111111:result=B-A;
6'b110110:result=-A;
6'b001100:result=A&B;
6'b011100:result=A|B;
6'b010000:result=0;
6'b110001:result=1;
6'b110010:result=-1;
default:result=0;
endcase
end
endmodule

//code for shifter
module shifter(C,sll,sr,Alu_Out,clk);
output  reg [0:31]C;
input clk;
input sll,sr;
input  [0:31]Alu_Out;
integer i;
always @(posedge clk)
begin
if(sll==1'b1 && sr==1'b0)
    begin
        for(i=0;i<24;i=i+1)
            begin
            C[i]<=Alu_Out[i+8];
            end
        for(i=31;i>23;i=i-1)
            begin
            C[i]<=0;
            end
    end
if(sll==1'b0 && sr==1'b1)
    begin
    C[0]<=Alu_Out[0];       
    for(i=0;i<31;i=i+1)
            begin
            C[i+1]<=Alu_Out[i];
            end
    end
end
endmodule

I am trying to implement the IJVM using verilog i.e. given in Tanenbaum textbook , for which I am making the ALU unit and the shift register, I have made the ALU and shift register unit separately and now I want to combine both the units i.e I want to give the output of ALU i.e. "result"(please refer to the code) as the input to the shifter i.e. "Alu_out"(please refer to the code).And get the final output form shifter i.e. "C"(please refer to the code). Can anybody please help to solve this issue and how to write the test bench for the same.

How to connect modules look at https://stackoverflow.com/questions/48353029/using-outputs-from-two-other-module-verilog/48355725#48355725. As to how to write the test-bench: you have to do that yourself, but we are willing to help if you have a *specific* issue. — Oldfart, May 26 '18 at 22:20

score 0 · Accepted Answer · answered May 27 '18 at 07:37

Call module alu in your module shifter

module shifter(C,sll,sr,Alu_Out,clk,A,B,control);
output  reg [0:31]C;
input clk;
input sll,sr;
input [0:31] A;
input [0:31]B;
input [0:5]control;
input  [0:31]Alu_Out;

alu first_call(Alu_out,A,B,control);

your rest code
value of result from first module will be stored in alu_out and give the inputs in shifter module itself. You can also make alu function as you need just one output as result.

How to give the output of one module to be used as an input by another module in verilog?

1 Answers1