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I'm doing a research about how memory is managed in RTEMS using an ARM-based Xilinx Zynq. The program runs on two cores with SMP.

I have read about memory barriers and out-of-order execution paradigm, I concluded that a barrier or a fence is a hardware implementation rather than software.

RAM is divided in several sections, however there are some sections called barriers which shared areas with other sections. I attach you a capture.

start-text-barrier

xbarrier starts where the next section begins and ends where previous section ends. Another example:

rwbarrier

In this one, the barrier starts at the same addres as the previous section and it ends before the next section starts.

Are these memory sections related with barrier instructions? Why are these memory sections implemented?

Thanks in advance,

ferdepe
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  • I assume that is implementation defined, what do your fpga/hardware engineers say about those memory regions? – old_timer Mar 15 '18 at 14:30

2 Answers2

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Googling "section .rwbarrier" will get you to https://lists.rtems.org/pipermail/users/2015-May/028893.html, which says:

This section helps to protect the code and read-only sections from write access via the MMU.

Arch D. Robison
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It looks like this is not linked to barrier instructions at all. Could it be a section of memory which is called like this just to separate a region which is read-write from a region which is read-only (vector) ?

The barrier instructions are used to force order in a multiprocessor system, they will never be linked to an address. The barrier instruction is used to split the visibility (For other CPUs or threads) between:

  • Load and store instructions before the barrier
  • Load and store instructions after the barrier.
Dric512
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