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I read that in multiprocessor system each processor has its own copy of interrupt descriptor table (IDT) and they use one copy of global descriptor table (GDT).

Why processors can't use one copy of IDT?

vvebik
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1 Answers1

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I assume from the use of the term GDT that you are asking about an x86 and/or x86-64 processor.

Each x86 processor (hardware thread, to be precise) has its own separate IDTR and GDTR registers. This allows, but does not require, the OS to use a distinct IDT and GDT on each processor.

The interrupt vector space in x86 is 8 bits, of which 32 are reserved, leaving 224 interrupts. In many platforms this is not enough distinct interrupt vectors. By using a distinct IDT on each processor, the OS can assign up to 224 distinct interrupt vectors per processor. (However, you should not assume that all OSes do this.)

In contrast, the GDT can hold up to 8191 descriptors*, which is far, far more than most OSes use, so there is rarely any need for an OS to use separate GDTs on each processor.

* GDT entry 0 cannot be used, because a selector with index 0 is considered a null selector. In 64-bit mode, system descriptors are extended to 16 bytes, while code and data descriptors remain 8 bytes, so the total number of entries possible in the GDT depends on the types of descriptors present.

prl
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  • The 16-bit table-size field of [the size:pointer operand for `lgdt`](https://github.com/HJLebbink/asm-dude/wiki/LGDT_LIDT) is encoded as `bytes - 1`, so you can pass a size of 65536 bytes / 8192 descriptors. Segment selectors of `0xfff8 | priv_level` should index the highest one. Is there some other limitation that prevents you from using all 8192 GDT or LDT entries? – Peter Cordes Jan 16 '18 at 08:52
  • And BTW, Intel's manuals use the name `GDTR` for the internal GDT-pointer register set by `lgdt`, and same for IDTR / LDTR. – Peter Cordes Jan 16 '18 at 08:53
  • heh, I wondered if it was something simple like that, thanks. – Peter Cordes Jan 16 '18 at 16:57
  • Being pedantic, but in 64-bit mode the number of descriptors may be lower when TSS descriptors are present as they are 16 bytes wide (and not 8 bytes) – Michael Petch Jan 17 '18 at 21:03