Kind on hard-simple question, i know it's general but that is exactly why i am asking...
if i write a code in vhdl and i use a process which starts this way:
Process(clk,x,y,x)
begin
...
end process
is there any way which in i won't have to save x,y,z values ? the way i understand this, if i wont save them, i wont be able to say if one of them changed which means i have to save them.
im writing assignment with a friend for university and we have different opinions. thanks a lot for helpers !
It totally depends on your needs.
In case you don't know - when you make some project in VHDL for FPGA, CPLD etc. you have to forget about what you knew about programming, because you are designing hardware, not software. You mostly, if not always, you don't have to save this values, for example when you make combinatorial circuit. In this case you don't care what was before, but only what this value is currently. Look at some examples with finite states machines, that has process with combinatorial logic.
And lastly – if you put clock to sensitivity list, it means that you want it to be synchronous, and process will launch only on some edge of this clock, so putting any more signals to it (with exception for reset) is pointless.
