T-flip flop in Verilog

Question

I want to build a T-flip flop in Verilog. So far I have written the following code, but I wish they could see if it is correct please. The machine I was using to make the code is in the image.

module flopJK(q,j,k,c);
 input j,k,c;
 output q;
 reg q;
 always @(posedge c)
 begin
  case ({j,k})
   {1'b0,1'b0}:begin q=q; end
   {1'b0,1'b1}:begin q=1'b0; end
   {1'b1, 1'b0}:begin q=1'b1; end
   {1'b1, 1'b1}:begin q=~q; end
  endcase
 end
endmodule

T-flip flop in Verilog:

score 1 · Accepted Answer · answered Mar 26 '17 at 15:57

1

There are several scope of improvements I think.

reset signal is not there, which is required to initialise your FF.
Always use non-blocking assignment for sequential logic and blocking for combinational logic.

Here is your code.

module flopJK (q,j,k,c, r);
 input j,k,c, r;
 output q;
 reg q;

 always @(posedge c, negedge r)
 begin
  if (r != 1) 
     q <= 1'b0;
  else
  begin
    case ({j,k})
     {1'b0,1'b0}:begin q <= q; end
     {1'b0,1'b1}:begin q <= 1'b0; end
     {1'b1, 1'b0}:begin q <= 1'b1; end
     {1'b1, 1'b1}:begin q <= ~q; end
    endcase
  end
 end
endmodule

answered Mar 26 '17 at 15:57

Karan Shah

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Thanks. Could you make the code for a scale T whose signal starts at Q1 = 0 and Q0 = 0 please? I am a beginner and my teacher takes some things as given and I can only learn by seeing things. – Carmen González Mar 26 '17 at 16:49
You can add all signals with their starting value in reset block (if statement lf always block) – Karan Shah Mar 26 '17 at 17:00
But what do I write inside the case or the if? I'm a little lost. I really need help. I have never seen the code of a T-scale in Verilog. I'm starting from scratch. – Carmen González Mar 26 '17 at 17:08
What do you mean.by T scale? And it would be better if you start from verilog basics and then write this code. – Karan Shah Mar 26 '17 at 17:10
T scale = T flip flop. I do not speak english very well, but I always try to learn. I put the code of the flip flop T attached to the post. Could you check if the code is right, please? – Carmen González Mar 26 '17 at 18:06
yes it seems right. You can try your small designs on www.edaplayground.com – Karan Shah Mar 27 '17 at 03:55

T-flip flop in Verilog

1 Answers1