I get compile errors: data_out is not a valid l-value

Question

1. This is the module unit...

   module register_unit(data_out,data_in,load,clk,rst);
   parameter word_size=8;
   output [word_size-1:0] data_out;
   input [word_size-1:0] data_in;
   input load,clk,rst;
   reg data_out;
   
   always@(posedge clk or negedge rst)
     if(rst==0)
       data_out <= 0;
     else if(load)
       data_out <= data_in;
   endmodule
   

2. This is the test bench

   `include "register_unit.v"
   
   module test_bench();
   
   parameter word_size=8;
   
   reg clk,rst,load;
   reg [word_size-1:0] data_in;
   wire [word_size-1:0] data_out;
   
   register_unit m1 (.data_out(data_out),.data_in(data_in),.load(load),.clk(clk),.rst(rst));
   
   initial
   begin
     clk=0;
     forever begin
       #5 clk = ! clk; 
     end
   end
   
   initial
   begin
     rst=0;
     data_out=8'b0;
     load=0;
     #10 rst=1;
     load=1;
     #10 data_out=8'b00000100;
     #10 data_out=8'b00000101;
     #20 load=0;
   end
   
   initial
   begin
     $dumpfile ("register_unit.vcd");
     $dumpvars;
   end
   endmodule
   

3. I am compiling this code using iverilog command in linux.

4. iverilog -o register_unit.v register_unit_tb.v

5. While compiling the code it gives an error on data_out port it says it is invalid conversion.

6. Errors are data_out is not a valid l-value in test_bench and data_out is declared here as wire.

Answer 1

You can't assign a value to a wire in an initial block. In the initial block in your testbench, change data_out to data_in:

initial
begin
rst=0;
data_in=8'b0;
load=0;
#10 rst=1;
load=1;
#10 data_in=8'b00000100;
#10 data_in=8'b00000101;
#20 load=0;
end

I also got a compiler warning in register_unit. You should declare the reg using a bit width:

reg [word_size-1:0] data_out;