Verilog code for shift and add multiplier

Question

Good day guys, I'm created a Shift - And - Add multiplier. I'm confused on why my output is wrong and always at 85. Is it something with the Test bench ? It's working by the way.

new1.v

`define M ACC[0]
module mult4X4 (Clk, St, Mplier, Mcand, Done, Result);

input Clk,St;
input [3:0] Mplier, Mcand;
output Done;
output [7:0] Result;

reg [3:0] State;
reg [8:0] ACC;

initial
begin
    State = 0;
    ACC = 0;
end

always @(posedge Clk)
begin
    case (State)
        0:
            begin
                if(St == 1'b1)
                begin
                    ACC[8:4] <= 5'b00000 ;
                    ACC[3:0] <= Mplier ;
                    State <= 1;
                end
            end
        1,3,5,7 :
            begin
                if(`M==1'b1)
                begin
                    ACC[8:4] <= {1'b0, ACC[7:4]} + Mcand ;
                    State <= State +1;
                end
                else
                begin
                    ACC <= {1'b0, ACC[8:1]};
                    State <= State + 2;
                end
            end
        2,4,6,8 :
            begin
                ACC <= {1'b0, ACC[8:1]};
                State <= State +1;
            end
        9:
            begin
                State <= 0;
            end
        endcase
    end

    assign Done = (State == 9) ? 1'b1 : 1'b0 ;
    assign Result = (State == 9) ? ACC[7:0] : 8'b01010101;
endmodule

tb_new1.v

module tb_mult4X4;
    reg Clk,St,nReset;
    reg [3:0] Mplier;
    reg [3:0] Mcand;
    wire Done;
    wire [7:0] Result;

    mult4X4 UUT (Clk,St,Mplier,Mcand,Done,Result);

    initial begin
        $dumpfile ("mult4X4.vpd");
        $dumpvars;
    end
    initial
        Clk = 0;

    always
        #5 Clk =~Clk;
    initial begin

        nReset = 0;
        St = 0; 
        Mcand = 4'b1101;
        Mplier = 4'b1011;

        #10
        nReset = 1;
        St = 1;
        Mcand = 4'b1111;
        Mplier = 4'b1001;

        #10

        Mcand = 4'b0101;
        Mplier = 4'b1010;

        #10

        Mcand = 4'b1111;
        Mplier = 4'b1111;

        #10
        Mcand = 4'b1101;
        Mplier = 4'b1010;

        $finish;
    end
endmodule

I ran though the code so many times and everything seems to be following my FSM. Can anyone please point out where went wrong. Really confused on this one

score 0 · Answer 1 · answered Oct 02 '16 at 23:17

#10 is way to short. Your RTL requires 10 clocks to complete but you change the input every clock (half clk is #5). Use #100 or better yet @(posedge Done); (which makes the test-bench to wait for done regardless the number of clocks that is required).

Verilog code for shift and add multiplier

1 Answers1