Verilog error : Unable to bind parameter in module

Question

I'm new to Verilog, I'd really appreciate it if someone could help me figure this error out:

I'm trying to write a test bench PU_tb, which is instantiating this module:

PU_conv #(
.image_width         ( image_width        ),
.image_height        ( image_height       ),
.kernel_width        ( kernel_width       ),
.kernel_height       ( kernel_height      )
) convolution (
.ACLK               ( ACLK                ), //input    
.image              ( image               ), //input
.kernel             ( kernel              ), //input
.result             ( result              )  //output    
);

The module PU_conv looks like this:

module PU_conv 
#( //Parameters
parameter integer image_width   = 10,
parameter integer image_height  = 4,
parameter integer kernel_width  = 2,
parameter integer kernel_height = 2
)( //PORTS
input   wire                                   ACLK,
input   wire [0:image_width][image_height:0]   image,
input   wire [0:kernel_width][kernel_height:0] kernel,
output  reg [0:image_width][image_height:0]    result
);

I'm getting this error:

error: Unable to bind parameter 'image_height' in 'PU_tb'
error: Unable to bind parameter 'image_width' in 'PU_tb'
error: Unable to bind parameter 'kernel_height' in 'PU_tb'
error: Unable to bind parameter 'kernel_width' in 'PU_tb'

The kernel and image widths and heights are declared as follows:

reg[5:0] param_kw;
reg[5:0] param_kh;
reg[5:0] param_iw;
reg[5:0] param_ih; ....

integer kernel_width, kernel_height, image_width, image_height;
always @(param_kw)
    kernel_width = param_kw;
always @(param_kh)
    kernel_height = param_kh;
always @(param_iw)
    image_width = param_iw;
always @(param_ih)
    image_height = param_ih;

What am I doing wrong?

score 1 · Accepted Answer · edited Apr 13 '17 at 12:32

The following code works fine. Make sure you have declared parameters correctly in top/tb module.

module PU_conv 
#( //Parameters
parameter integer image_width   = 10,
parameter integer image_height  = 4,
parameter integer kernel_width  = 2,
parameter integer kernel_height = 2
) ( //PORTS
input   wire                                   ACLK,
input   wire [0:image_width][image_height:0]   image,
input   wire [0:kernel_width][kernel_height:0] kernel,
output  reg [0:image_width][image_height:0]    result
);

initial
begin
$display("image_width = %0d image_height = %0d",image_width,image_height);
$display("kernel_width = %0d kernel_height = %0d",kernel_width,kernel_height);
end
endmodule 

module top();

parameter integer image_width   = 8;
parameter integer image_height  = 7;
parameter integer kernel_width  = 6;
parameter integer kernel_height = 5;

wire                                   ACLK;
wire [0:image_width][image_height:0]   image;
wire [0:kernel_width][kernel_height:0] kernel;
reg [0:image_width][image_height:0]    result;

PU_conv #(
.image_width         ( image_width        ),
.image_height        ( image_height       ),
.kernel_width        ( kernel_width       ),
.kernel_height       ( kernel_height      )
) convolution (
.ACLK               ( ACLK                ), //input    
.image              ( image               ), //input
.kernel             ( kernel              ), //input
.result             ( result              )  //output    
);
endmodule

Multi dimensional arrays as inputs are supported in SystemVerilog only. Following is the output display:

// Overridden parameters
image_width = 8 image_height = 7
kernel_width = 6 kernel_height = 5

Similar question is posted in Verilog Parameter over ridding.

Thank you, I didn't know about multi dimensional arrays not being supported as inputs! I've declared the variables as shown in the code. Is there anything wrong with that? It still says unable to bind parameter. — AnnaR, Jul 04 '16 at 07:39
You need to have `kernel_width, kernel_height, image_width, image_height` as parameters rather than variables. Since parameters are evaluated at **elaboration time**, you either need to have parameters or macro-values. — sharvil111, Jul 04 '16 at 08:40
If I declare them as parameters, I get the error _Syntax error parameter list_ — AnnaR, Jul 04 '16 at 16:36
Point out where the exact error is. Make sure that there is a semi-colon(;) after parameter declaration and not a comma (,). Copy-paste the code given in my answer and changes your values accordingly. The code works fine for me. — sharvil111, Jul 05 '16 at 01:37

Verilog error : Unable to bind parameter in module

1 Answers1