How to call tasks from a separate module in Verilog?

Question

I'm new to Verilog and would really appreciate it if someone could help me with this.

I have a task written in a separate file - "task.v" :

module task_create();

task assign_inp;
    reg a,b,c,d;
    //details
endtask

endmodule

I have a module that is calling this task:

module tb();
    `include "task.v"
    assign_inp(a,b,c,d);
endmodule

When I execute this, I get this error:

Module definition task_create cannot nest into module tb

When I remove the module and endmodule in task.v, I get this error:

Task must be contained inside a module

Where am I going wrong? Thank you so much!

score 1 · Accepted Answer · answered Jun 03 '16 at 23:57

1

Your task in in a module and so can only be seen in the module. What you can do is remove the module wrapper and just declare the task in a separate file.

task assign_inp;
    reg a,b,c,d;
    //details
endtask

You can include the task and you should be able to see the task.

Removing the modules works for me.

EDIT: You may need to declare the verilog file as a header file for the task

answered Jun 03 '16 at 23:57

okebz

132
1
8

I tried doing what you said. I removed the module wrapper used ` `include "task.v"` `module tb();` `assign_inp(a,b,c,d);` `endmodule` But am still getting the error _task declarations must be contained inside a module_ – AnnaR Jun 04 '16 at 00:14
put the include statement inside the module declaration. – okebz Jun 04 '16 at 00:36
I'm really sorry, these questions are probably silly, but I'm still getting the same error! – AnnaR Jun 04 '16 at 00:44
What simulator are you using? – okebz Jun 04 '16 at 00:47
I'm using iverilog – AnnaR Jun 04 '16 at 00:48
You might be including the task.v as a verilog source when you compile. If you are, don't include it in the list of sources that you compile, but include the directory so the compiler knows where the include file is located using the -I option – okebz Jun 04 '16 at 00:54
When I try that, I get unknown module type: assign_inp, these modules were missing - assign_inp – AnnaR Jun 04 '16 at 01:01
Oh, this is because you are instantiating the task like a module. Tasks are called with a statement such as inside an initial or an always block. – okebz Jun 04 '16 at 01:28

How to call tasks from a separate module in Verilog?

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