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i want to find a single max value for an input signal that has 1000 decimal values that is read from a memory once every Positive clk edge.i did the following rough code for finding max value but it didn't give me the correct max value/number please help me so i can find a single max value in these 1000 values of input signal..`thanks in advance

module(input clk, input [15:0]din, output [15:0]dout);
reg [15:0] max=0;

always @ (Posedge clk)
if(din>max)
max<=din;
else
max<=0;

assign dout=max;
endmodule
MR.simple
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  • You might use a **counter** to count 1000 samples. Currently, there is no provision for taking into account 1000 **latest** input values. Also, you need **store** those 1000 samples (memory). Each time the input changes (some combinational block), compare the present input with each of those 1000 samples. – sharvil111 May 25 '16 at 06:08
  • As a side note, use non-blocking assignments (`<=`) in sequential blocks. Also, the keyword `posedge` needs to be in lower-case letters. – sharvil111 May 25 '16 at 06:08
  • Sharvil111 thanks for your reply..if u don't mind can u edit my code by writing code for counter to count these values and then i can find single max value.. – MR.simple May 25 '16 at 06:11

2 Answers2

1

Assumption 1:

If your memory read operation of 1000 valuation is out of your finding max value module then no need to track how many values are read. 

module find_max (input         clk, 
                 input  [15:0] din, 
                 output [15:0] dout
               );

reg [15:0] max=0;

always @ (posedge clk)
begin
  if(din > max)
    max <= din;
  else
    max <= max;
end

assign dout = max;

endmodule

Your max value reflected in output after next cycle of being fed to find_max module.

Assumption 2:

If your outof find_max module not taking care of total number of valuation read then we just required one counter which track the number of cycles or valuation arrived.

module find_max (input         clk, 
                 input  [15:0] din, 
                 output [15:0] dout
               );

reg [15:0] max=0;
reg [ 9:0] cnt=0;

always @ (posedge clk)
begin
  cnt <= cnt + 1'b1;
  if(din > max)
    max <= din;
  else
    max <= max;
end

assign dout = (cnt == 10'd1000) ? max : 16'd0;

endmodule

We need not to store value of 1000 sample because we have to find only max value.

Prakash Darji
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  • Prakash Darji..thanks for your time..i try yours code for my din signal but dout shows 0..it didn't maximum value.. i am attaching my test bench code plzz have a look on it.. – MR.simple May 25 '16 at 08:31
  • upload your mem file – Prakash Darji May 25 '16 at 09:00
  • First try to read data from file. See you are not fetching data from file properly, check it first and then see. – Prakash Darji May 25 '16 at 09:06
  • You haven't created clock also. make proper tb and then see the result. – Prakash Darji May 25 '16 at 09:22
  • @PrakashDarji. `reg [15:0] max=0;` is this valid ? I haven't come across double assignments for a reg ( max is also assigned inside always block). Can provide me any reference to read this ? – Sourabh May 27 '16 at 06:45
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You don't need to assign a value to max when din<=max as in else statement.

module(input clk, input [15:0]din, output reg [15:0]dout); always @ (posedge clk) if(din>max) max<=din; endmodule

Sourabh
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