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I want to initialize a byte array (or any other possible type) to a long string. For example define: string str = "abcdefg". I read these two links (Link 1 & Link 2) but I couldn't find a simple way. These are two hard code ways which I found:

1_ byte str [0:7]; = '{"a", "b", "c", "d", "e", "f", "g", "h"}; This is not an appropriate way, because the string is very long in my real application and I can't write them letter by letter.

2_ Using string type :string str = "abcdefg". But it can only be simulated and isn't synthesizable. Quartus just allows defining string in function or task. So I use the function getStr() for initializing string :

typedef byte string_t[0:7];

function string_t getStr();
    int i;
    string tmp_str = "abcdefgh";            
    string_t str;

    for(i=0; i<8; i=i+1)
        str[i]=tmp_str[i];

    return str;
endfunction

and use it in my code : 

byte str [0:7];
always @(posedge clk) begin 
     str = getStr(); // str will be "abcdefg" after getStr() return it.
     //The rest of the code...
end

I think there must be a better and simpler way for initialize a string in SystemVerilog. If you know it help me. Thanks.

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Soheil Shababi
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    The answare is in [this link](http://electronics.stackexchange.com/questions/228686/how-can-assign-a-synthesizable-string-to-a-byte-array-in-systemverilog/228779#228779)... – Soheil Shababi Apr 17 '16 at 11:49

1 Answers1

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You can initialise a packed array using a string:

bit [0:87] BIT_ARRAY = "Hello world";

Is that close enough? If you really need it to be an unpacked byte array then you'll have to convert it.

Matthew Taylor
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  • Yes, I need to use unpacked byte array because after the initialization, I have to read every letter of string, letter by letter. With using byte array it can be simply read for example 4th letter: `byte fourth = BYTE_ARRAY[3]`. Although it's not easy to read letters of bit array (for reading 4th we have to read bits from 24 to 31). Can you please complete your solution with describing how can convert bit array to byte array ? – Soheil Shababi Apr 16 '16 at 14:27
  • I found a way for convert bit array to byte array [here](https://books.google.com/books?id=fnnx2iH_4XYC&pg=PA56&lpg=PA56&dq=convert+bit+array+to+unpacked+byte+array&source=bl&ots=du2LzKzgeK&sig=2bdKOr5B7I6N945FSjx24JWwGZE&hl=en&sa=X&ved=0ahUKEwjPw7yTp5PMAhUCEJoKHU0sDewQ6AEIIjAB#v=onepage&q=convert%20bit%20array%20to%20unpacked%20byte%20array&f=false), but it can't be synthesized in Quartus, it just can be simulated in Modelsim. `bit [63:0] bit_array = "abcdefgh";` `byte str [0:7] = { >> {bit_array}};` – Soheil Shababi Apr 16 '16 at 14:33
  • @saman samani Yes, I thought of those streaming opeators, but didn't think they would be synthesisble. I would have thought converting in a `for` loop as @sharvil111suggested would do the trick and be synthesisable (I don't have a syntehsiser at hand to check). – Matthew Taylor Apr 17 '16 at 13:14
  • I believe, streaming operator are synthesizable. You can read the following link for synthesizable SV constructs - http://www.sutherland-hdl.com/papers/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf – Karan Shah Apr 23 '16 at 15:19