Value changes based on clk doesn't work for random numbers

Question

I am coding that put the value of 'd' into 'z' whenever 'clk' is changed to '1'.

For example,

clk=0 d=        15, z=         x
clk=1 d=        20, z=        20
clk=0 d=        25, z=        20
clk=1 d=        30, z=        30

it put value of 'd' into 'z' whenever clk is '1'.

So below is code that does repeat it for 20 times for random numbers.

module lab9;
reg [31:0] d;
reg clk, enable, flag;
wire [31:0] z;
reg [31:0] e;
register #(32) mine(z, d, clk, enable);

always begin
#5 clk = ~clk;

end

initial
#1 $monitor("%5d: clk=%b,d=%d,z=%d,expect=%d", $time,clk,d,z, e);

initial begin 
clk=0;
flag = $value$plusargs("enable=%b", enable);

repeat (20) begin
#2 d = $random;
end
$finish; 

end 

endmodule

And the output I get:

    1: clk=0,d=         x,z=         x,expect=         x
    2: clk=0,d= 303379748,z=         x,expect=         x
    4: clk=0,d=3230228097,z=         x,expect=         x
    5: clk=1,d=3230228097,z=3230228097,expect=         x
    6: clk=1,d=2223298057,z=3230228097,expect=         x
    8: clk=1,d=2985317987,z=3230228097,expect=         x
   10: clk=0,d= 112818957,z=3230228097,expect=         x
   12: clk=0,d=1189058957,z=3230228097,expect=         x
   14: clk=0,d=2999092325,z=3230228097,expect=         x
   15: clk=1,d=2999092325,z=2999092325,expect=         x
   16: clk=1,d=2302104082,z=2999092325,expect=         x
   18: clk=1,d=  15983361,z=2999092325,expect=         x
   20: clk=0,d= 114806029,z=2999092325,expect=         x
   22: clk=0,d= 992211318,z=2999092325,expect=         x
   24: clk=0,d= 512609597,z=2999092325,expect=         x
   25: clk=1,d= 512609597,z= 512609597,expect=         x
   26: clk=1,d=1993627629,z= 512609597,expect=         x
   28: clk=1,d=1177417612,z= 512609597,expect=         x
   30: clk=0,d=2097015289,z= 512609597,expect=         x
   32: clk=0,d=3812041926,z= 512609597,expect=         x
   34: clk=0,d=3807872197,z= 512609597,expect=         x
   35: clk=1,d=3807872197,z=3807872197,expect=         x
   36: clk=1,d=3574846122,z=3807872197,expect=         x
   38: clk=1,d=1924134885,z=3807872197,expect=         x
   40: clk=0,d=3151131255,z=3807872197,expect=         x

On Line 6 of this output need to be '2223298057' but still have value of previous 'z' even though its clk is set to '1'.

How can I fix this?

@toolic I thought problem is inside of my code since register isn't what I even have, thus, is kinda provided by Verilog system. therefore I guess my code is not good to properly work with register. — online.0227, Mar 22 '16 at 20:25

score 1 · Answer 1 · answered Mar 22 '16 at 20:22

Your register is already working correctly. Registers are edge-triggered; there is no clock edge between time steps 5 and 6, so the value of z is not updated.

If you want z to be updated continuously as long as the clock is high, you want a latch, not a register. Be forewarned, however, that timing analysis is much more difficult in designs which include latches, and as such they should usually be avoided.

Matthew Taylor · Accepted Answer · 2016-03-22T22:05:25.740

1

It would seem from the behaviour of the outputs you have presented that

register #(32) mine(z, d, clk, enable);

is a set of 32 D-type flip-flops, which given its name and the names of the signals you have connected also seems to be the case. It would have been easier to answer your question if you had provided the code for register.

So, if register is indeed a set of 32 D-type flip-flops, you would not expect z to change at time 6. That is not how any kind of flip-flop behaves: the output of a flip-flop only changes on one (rising or falling) edge of a clock.

Given these D-type flip-flops were present before you started this exercise, it would seem that you are changing d far too quickly. You ought to be changing it once per clock (clk) cycle, ie once every #10. In other words, try chaninging

#2 d = $random;

to

#10 d = $random;

edited Mar 22 '16 at 22:05

answered Mar 22 '16 at 20:26

Matthew Taylor

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stangely I don't have any source code for register. (I do not have file named register.v in the same folder of this source code as well, also, outside as well) It just compile s and run, even tho output is not the one I wanted. – online.0227 Mar 22 '16 at 20:41
@online.0227 What is the full command you are using to compile and run your simulation? If you are driving it from a GUI, then the command might be the first thing in the simulator output. – Matthew Taylor Mar 22 '16 at 20:59
iverilog -o circuit lab9_part2.v && vvp circuit +enable=1 – online.0227 Mar 22 '16 at 21:12
I run this on linux system's terminal – online.0227 Mar 22 '16 at 21:13
@online.0227 Thanks - unfortunately, it doesn't help. I was hoping that their would be some kind of indication where the code for `register` was in the command. Well, it is almost certainly a set of flip-flops, and given you didn't write that code, that is what is intended to be there? Did you instantiate `register` or was it already there in the file `lab9_part2.v`? – Matthew Taylor Mar 22 '16 at 21:33
I really didn't do a single thing except than the source code I provided above and compile and run it with the command above on terminal. I don't get the meaning of what you said, instantiate register, but I really didn't do other than the source code above. – online.0227 Mar 22 '16 at 21:46
@online.0227 I mean: did you type the line `register #(32) mine(z, d, clk, enable);`? Or was it already in the file before you started editing it? – Matthew Taylor Mar 22 '16 at 21:48
yes. it was already there just like you see on the source code above. Thank you. (in fact I wrote down that into my source code by myself as I am going through the manual. But I did only that. I didn't do write it other than my source code. – online.0227 Mar 22 '16 at 21:53
@online.0227 So, if that line was already there, then, as I said in my answer, you are not understanding the behaviour of a D-type flip-flop. It would seem like you are expecting it to behave like a latch. I would say you are changing D far too quickly; you should be changing it once per clock (`clk`) cycle, ie every `#10`. I will update my answer to reflect this. Please rate it if you find it helpful. – Matthew Taylor Mar 22 '16 at 21:57
Ok you mean like i have to put "#10" in front of "register #(32) mine(z, d, clk, enable);" ? the instructor doesn't tell me about D-type flip-flop maybe i need to study it first. Thank you very much. – online.0227 Mar 22 '16 at 22:02

Value changes based on clk doesn't work for random numbers

2 Answers2