3

Let's say module_a has register_a in it, which needs to be linked to module_b. Should register_a be declared separately and assigned to an output of module_a:

reg register_a;
assign output_a = register_a;

or should we just declare output_a with a reg inline in the module declaration and use that in the code?

Hassaan
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3 Answers3

8

I think you are asking about the difference between the following:

module my_dff (output reg q, input clk, d); //None Blocking style
  always @(posedge clk) begin
    q <= d;
  end
endmodule

vs

module my_dff (output q, input clk, d);
  reg reg_q;
  assign q = reg_q; // Blocking style
  always @(posedge clk) begin
    reg_q <= d;
  end
endmodule

Between the two, there is no functional difference. It is mostly a coding preference. There are a hand full of simulators that do not enforce directional of inputs and outputs, so if a there are accidentally two modules driving the same net, those simulators an X can propagate X to the register with output reg. This is a rare scenario, most simulators (especially the mainstream ones) don't have this issue.

I personally prefer output reg mainly because it is fewer lines of code.

Regardless of how the output type is declared, when you instantiate the module, the output needs to be connected to a net-type (eg wire), not a reg. Inputs can be either type. 

module fifo(output out, input clk, in);
  wire q0;
  reg q1;
  my_dff dff0 ( q0, clk, in );
  always @(posedge clk) begin
    q1 <= q0;
  end
  my_dff dff1 ( out, clk, q1 );
endmodule
Michael
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Greg
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1

I'm assuming you're looking for something like this:

module module_b (...);
    ....
    module_a foo (.output_a(some_wire),
                  ...);
endmodule

If that's the case, then it doesn't matter - both versions will produce the same resulting circuit.

The first method does have some advantages, namely that you can gate the output (something like assign output_a = valid ? register_a : 0;) if you wanted, and are able to work internally with the name of your choice if the interface is defined for you (like a preset pin mapping, for example).

If you're not trying to do the above, than this might not be true.

wilcroft
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0

I read that outputs should always be registered. That is to say that module_a has an output named output_a. This is a behavioral vs sequential code style. It is true you can create the same hardware either way but I think the answer to your question is you should declare the output as a reg.

so the module declaration would be something like:

module module_a (output reg output_a);
....
output_a <= "some value"
endmodule
Michael
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  • It is good practice to register the outputs of significant blocks (eg a top-level block or a block that will be synthesised separately). By "register", this means pass those outputs through a flip-flop (not a Verilog `reg`). It is not necessary to register the outputs of every module. However, much more importantly, a verilog `reg` is **not** a flip-flop. So, if you did think that is the case, please disavail yourself of that idea. – Matthew Taylor Feb 27 '16 at 20:34
  • A flip flop is to say use memory correct? Which is what reg is for... for memory. I will do some further research to see if that is not the case but when you get an always block involved it's good practice to sync. But I digress the difference in the top answer is that there is a continuous assignment. Why then go to an assignment on the clock? kind of defeats the purpose so there is a difference in code conventions. – Michael Feb 28 '16 at 22:21
  • @Micahel No, it is not correct. A `reg` is a Verilog variable (as opposed to a `wire` which is a net). A reg is just like a variable in any other language: the last value assigned to it is the value it has. You can use a `reg` to infer both combinational or sequential logic. – Matthew Taylor Feb 29 '16 at 17:39
  • registering outputs is wonderful but really, "always" is not true. It is an easy path to easier timing closure in high speed systems. But that is why "they" say that – johnnymopo Jun 15 '20 at 22:21