Verilog generate statement with always@(*) block

Question

I have this generate block below which I think should work, but I am seeing issues with the always @(*) part under the else block. When using VCS, temp_in[i+1][j] is assigned 'x' always. I expect it to be set to '0'. If I instantiate a module/gate instead of always block, like I did for the if part, then it works correctly. Googling for the right syntax for using foreach, generate, always and if within a single block does not yield any useful results. I know the fix is a minor change but I am not that familiar with all the language constructs, so I will appreciate any help.

ceil() is a function which returns an integer. It uses only parameters which are fixed at compile time, so I expect the loop unrolling to happen correctly.

  genvar i, j, k;
  generate
    for (i = 0; i < NUM_STAGES; i = i + 1) begin:gen_stage
      for (j = 0; j < (TOTAL_LENGTH/(2**(i+1))); j = j + 1) begin:gen_or
        if(j < ceil(i)) begin
          for (k = 0; k < CPU_DATA_WIDTH; k = k + 1) begin:gen_bit
            msw_mem_out_mux_bit_or U_msw_mem_out_mux_bit_or (
              .in_1 (temp_in[i][2*j][k]),
              .in_2 (temp_in[i][(2*j)+1][k]),
              .out  (temp_in[i+1][j][k])
            );
          end
        end else begin
          always @(*) begin
            temp_in[i+1][j] = {CPU_DATA_WIDTH{1'b0}};
          end
        end
      end
    end
  endgenerate

Greg · Accepted Answer · 2017-12-18T21:02:02.433

An always @* waits until a change occurs on a signal in the inferred sensitivity list. i and j are constants (from the perspective of simulation time when always @* is evaluating), so the your always block has no signals in the sensitivity list.

If using SystemVerilog, change always @* to always_comb which will run at time 0. For Verilog, add an initial block.

Reference: IEEE Std 1800-2012 § 9.2.2.2.2 always_comb compared to always @*

Verilog generate statement with always@(*) block

1 Answers1