I am building a divider for my MIPS processor ALU for integer division, and also in FPU for single precision floating point division purpose. I have searched lots of algorithms and wanted to find a good solution.
Since the design is implemented in FPGA, and Altera DE2 is the board I am going to use. Its has many embedded multipliers. Therefore, I think Newton-Raphson method is quite good for my design, the algorithm only need multiplier and adder.
As a Chinese, my English is not very good. After a long time pain of reading the Newton-Raphson paper on Google, I only got results:
if Q=a/b => Q=a * 1/b
and the approximately result Xi+1 = Xi(2 - bXi )
From now, it looks like very clearly, we only need do two multiplications and one subtraction to get a X. What I didn't got from those paper are(Maybe they already on the paper, in some sort of complex equations. As I said my English is bad and that just hard for me to understand those high level paper):
1: How many iterations in one division I need to get a 32-bit integer and 32-bit IEEE754 floating point?
2: What is the initial X? I have searched Newton-Raphson lookup table on Google, but I can't find any good information.
3: What is the "FMA"? I mean in term of logic circuit schematic.
If some give me a floating point division tutorial, It will be very grateful.