Concatenated vector is truncated in synthesis

Question

In attempting to concatenate a 32-bit floating point vector for a linear function shift register all goes well in behavioral simulation. However, in post-synthesis the "random_float" net has been truncated to 31 bits. It seems the "sign" is getting ignored. Any ideas?

logic       [7:0]   exponent_seed      =   8'b01100101;
logic       [22:0]  mantissa_seed      =   23'b01001011101011110010100;
logic       [31:0]  random_float       =   32'b00000000000000000000000000000000;
logic       [7:0]   exponent           =   exponent_seed;
logic       [22:0]  mantissa           =   mantissa_seed;
logic               sign               =   1'b0;  

wire                exponent_feedback  =   exponent[7] ^ exponent[5] ^ exponent[4] ^ exponent[3];

always @ (exponent or mantissa or sign)
    begin
        random_float <= {sign, exponent, mantissa};
    end

 always @ (posedge clk or posedge reset)
    begin
        if (reset)
            begin
                exponent        <= exponent_seed;
                mantissa        <= mantissa_seed;
            end
         else
            begin
                //use concatenation to shift and feed the vector.
                exponent <= {exponent[6:0], exponent_feedback};
                mantissa <= {mantissa[21:0], mantissa_feedback};
            end
    end

PS i've only included what i believe to be the relevant code.

`sign` is constant and optimized away (I don't know if this is a good translation...) Due to constant propagation the signal / bit was removed. Simulators do this too, but sign can still be displayed in a waveform with a constant value. — Paebbels, Jul 16 '15 at 20:09
@Paebbels thanks! The full solution is to use (*KEEP = "TRUE" *) on "random_float" — jwanga, Jul 16 '15 at 22:57
why is sign constant? the issue would go away once you got to the point of handling signed floating points numbers. I assume the `KEEP="TRUE"` is a vivado pragma and not part of Verilog. — Morgan, Jul 17 '15 at 07:21
This was just an example. In the real code I need to generate a float within a certain range. As such, The least significant 6 bits are constant. — jwanga, Jul 19 '15 at 21:16
Note that assigning to signals declared as logic during declaration is not valid for combinational signals. Only wires could be initalized this way. For ASIC synthesis, having initial values for signals causes simulation/synthesis mismatch (synthesis would ignore those). For FPGA synthesis, inital values are only valid for registers only and not combinational logic. In your code, most inital value assignments to signals are not taken. For constants, I would use localparam instead. `localparam logic [7:0] exponent_seed = 8'b01100101;` — Amal, Jul 22 '15 at 18:39

score 2 · Accepted Answer · answered Jul 16 '15 at 22:59

2

For posterity the following prevents synthesis from optimizing out constants:

(*KEEP = "TRUE"*) logic       [31:0]  random_float       =   32'b00000000000000000000000000000000;

answered Jul 16 '15 at 22:59

jwanga

4,166
4
26
27

Concatenated vector is truncated in synthesis

1 Answers1