Systemverilog doesn't allow variable declarations after call to super.foo()?

Question

I'm running into a weird issue working with SystemVerilog on DVT. The code snippet in question looks something like this:

class parent;     

   int A;
   function void foo();
      A = 5;
   endfunction

endclass


class childA extends parent;

   function void foo();
      bit test_one; //Does not flag as a syntax error.
      super.foo();
      bit test_two; //Flags as error: Expected endfunction, found bit.
   endfunction      //Subsequently: Expected endclass, found endfunction

endclass            //And lastly: Unexpected token: Endclass

As far as I know it is legal to call any hidden parent function using super. but this behavior is perplexing me. Can someone tell me if this is legal SV syntax? Or if not: What's the reasoning behind this?

Greg · Accepted Answer · 2017-12-18T21:27:46.353

It is illegal syntax. All variables in a task or function must be declared before any operation. See IEEE Std 1800-2012 § 13 Tasks and functions (subroutines)

Legal syntax is:

function void foo();
  bit test_one;
  bit test_two;
  super.foo();
endfunction

The only exception is a begin-end block in which case the variable can be declared at the top of the begin-end block before any operation (but you can nest begin-end block). This does however limit scope access and may be less readable. So it not a good practice

function void foo();
  bit test_one;
  super.foo();
  begin
    bit test_two; // only in scope within this begin-end
    begin
     bit test_three; // not the same 'test_three' as below, different scope
    end
    begin
     bit test_three; // not the same 'test_three' as above, different scope
    end
    // both 'test_three's are out of scope
  end
  // 'test_two' both 'test_three's are out of scope
endfunction

General best practice is to always declare your variables at the top. I prefer adding empty space between variable declarations and operations a visual separator; makes reading and modifying a ascetically easier.

function void foo();
  bit test_one;
  bit test_two;

  super.foo();
endfunction

Systemverilog doesn't allow variable declarations after call to super.foo()?

1 Answers1