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I just need an explanation of how base + offset addressing modes work. Having trouble finding a clear-cut answer for this. (I've been working with the LC-3, not sure if that matters). A simple example would also be helpful.

Thank you!

Matt
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  • I believe I figured out the answer which is listed below. Thank for those who attempted to answer the question but the answers were not correct (at least in terms of the LC-3 architecture, I'm not sure, maybe base + offset works differently elsewhere). Anyone who is VERY familiar with the LC-3 and is confident in how base + offset addressing works, please review my answer below to see if it is correct. Thank you! – Matt May 05 '15 at 23:34

3 Answers3

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MOV EAX,[EBP+8]
MOV EBX,[EBP+12]

EBP is the base here (holds the base address) like "00402000" for instance so the EAX will be loaded with the value in the address [00402000+8] I.e 00402004

the accountant
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  • Not quite what I am looking for. In the LC-3, the base used is a register. The instruction for the LC-3 opcode looks like this: 0110 010 110 001101 The first four bits is the opcode (an LDR in this case); the next three is the destination register; the next three is the base register; and the last 6 is the offset (in 2's complement). If I am correct (and anyone please correct me if I am wrong), it takes the value of the base register, which is an address, adds the offset to it, and stores the value in the destination register, although I can't seem to get the correct answer. – Matt May 05 '15 at 22:17
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Base + Index addressing mode

2 Registers specify the address of an operand in an instruction. Add the numerical values stored in those registers to get the complete address of an operand.

Ex.
A = 1000
Register A = 1000
Register B = 8

MOV C, [A,B] => C = contents of location A+B

There is a flavor to Base + Indexing addressing called the base + Index + displacement

Displacement = immediate value in the instruction that is added to the Base + Index. thats what you see in your opcode.

instruction = OPCODE + Operand 1 Register Spec + Operand 2's Base Register Spec + Operand 2's Index Register Spec + Immediate value.

imagine a microprocessor with a 8 bit register space.

so a 16 bit operand may have

4 bit for opcode

3 bit for base register 3 bit for index register 6 bit for immediate displacement.

Thanks,

user_kpa
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  • I don't think this is correct. Based on what I have learned in class, I know that you are not adding the two registers together. The destination register is only used to store the calculated value and is not used as an operand. – Matt May 05 '15 at 23:12
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I believe I have figured out the answer. I'll post it here in case it helps anyone else who has trouble with this. I found the answer hidden deep in the 100 slide powerpoint that my teacher provided XD

This is what happens when performing an LDR using a base register R6 and destination register R2:

MAR<-R6 + IR[5:0]
MDR<-MEM[MAR]
R2<-MDR

Lets say R6 = x3000, IR[5:0] = x5, and R2 = 0 (although this value doesn't matter since it will be loaded with another value at the end)

MAR<-R6 + IR[5:0]

R6 is added to IR[5:0] (which is the offset value in the last six bits of the LDR instruction). The base x3000 (value of R6) has x5 (value of IR[5:0]) added to it, giving us x3005. The MAR (memory address register) now holds x3005.

MDR<-MEM[MAR]

The value in the MAR (x3005) is loaded into the MDR (memory data register). 

R2<-MDR

The value in the MDR (x3005) is loaded into R2. R2 now holds the value: x3005.

I hope this question helps those new to addressing modes like I am :)

Thank you all.

Matt
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  • "The value in the MAR (x3005) is loaded into the MDR (memory data register)." -- This seems wrong, the `MEM[MAR]` syntax probably means to load a value from the memory address given in the MAR. It does not mean to load the MAR value itself into the MDR. – ecm Mar 01 '20 at 17:44