How to test primality in Verilog?

Question

I have the Verilog code shown below, and if I try to compile it I get an error message. The point is that I'm trying to manipulate an input, which as long as I know cannot be done in Verilog. The point is that I need check the following condition in Verilog:

static int prime(unsigned long long n)
{
    unsigned long long val = 1;
    unsigned long long divisor = 5;

    if (n == 2 || n == 3)
        return 1;
    if (n < 2 || n%2 == 0 || n%3 == 0)
        return 0;
    for ( ; divisor<=n/divisor; val++, divisor=6*val-1)
    {
        if (n%divisor == 0 || n%(divisor+2) == 0)
            return 0;
    }
    return 1;
}

At the moment I have the following code:

module prime(clk, rst, start, A, ready, P);

input clk, rst, start;
input [7:0] A;

output ready, P;

reg ready, P;

wire [7:0] divisor;
assign divisor = 5;

wire [7:0] val;
assign val = 1;


always @ (posedge clk or posedge rst) begin
    if (!rst) begin
        P <= 0;
    end
    else if (start) begin
        case (A)
            0 : P <= 1;
            1 : P <= 1;
            2 : P <= 1;
            3 : P <= 1;
        endcase

        if (A%2 == 0 && A != 2) begin
            P <= 0;
        end
        else begin
            for( ; divisor <= A/divisor; val=val+1, divisor=6*val-1) begin
                if (A%divisor == 0 || A%(divisor+2) == 0) begin
                    P <= 0;
                end
            end

            // need to set P to 1
        end
    end
end

endmodule

Please also note I need to test primes in the form of 6n+1 or 6n-1, and I also need to assume in my code that 0 and 1 are also primes.

If I try the above code I get an error message saying:

Enhanced FOR loop is not enabled for verilog

If anyone can help me solve the error and finish my logic in Verilog, I would be glad.

Wait! Are you saying that 0 and 1 are primes? And instead of checking for `divisor <= A/divisor` you should use `divisor*divisor <= A` to avoid the division which is slow and takes much more space than multiplication — phuclv, Jun 28 '14 at 03:23
@LưuVĩnhPhúc I know that they are not prime. But in the task that I'm given I need to assume that they are prime, don't know even why. But yeah 2 is the smallest prime. — , Jun 28 '14 at 06:45

score 1 · Answer 1 · answered Jun 28 '14 at 00:54

1

The Verilog BNF does not allow empty or compound statements in for(;;). Change the file to *.sv to compile it under SystemVerilog rules. Otherwise change your for loop statement to have simple statements

for( divisor =5; divisor <= A/divisor; divisor=6*val-1) begin
                if (A%divisor == 0 || A%(divisor+2) == 0) begin
                    P <= 0;
                end
                val++;
            end

Also, you can't make procedural assignments to wires. make them variables.

answered Jun 28 '14 at 00:54

dave_59

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Also `var` isn't needed at all `for (divisor=5; divisor <= A/divisor; divisor=divisor+5) begin` – Greg Jun 28 '14 at 01:00
@Greg you cannot simply add 5 after each iteration. 5+5 = 10 and you don't need to check A % 10 at all. If needed you can use `for (step = 2, divisor = 5; divisor*divisor <= A; divisor <= divisor + step, step <= 6 - step)`. That would eliminate a multiplier. You can also alternating between a step of 2 and 4 – phuclv Jun 28 '14 at 03:31
2

The `+5` was a typo. I meant `+6`. – Greg Jun 28 '14 at 04:13

How to test primality in Verilog?

1 Answers1