In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

Question

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, why is the NAND connected to these 2 outputs and not the first and fourth since it's the first and fourth bits that are 1s.

An image of the circuit: http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/bincount.html (second one).

This question appears to be off-topic because it is about digital circuit design (try http://electronics.stackexchange.com). — Oliver Charlesworth, May 31 '14 at 10:21

score 0 · Answer 1 · answered Jun 01 '14 at 01:18

The RST input on these flip-flops is interpreted asynchronously (independently of CLK). If you trigger it on binary 9 on the output, the counter will be reset to 0 immediately. To have a full clock cycle with a 9 on the output, you trigger the reset on 10 (i.e. 1010).

In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

1 Answers1