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I'm trying to get a top-level makefile to call make in a number of subfolders. The top-level has several targets and the important bit is shown below: 

MAKE_DIRS := $(dir $(wildcard apps/**/Makefile))
.PHONY: clean_apps apps $(MAKE_DIRS)

clean_apps: TARGET_INFO := clean

apps clean_aps: $(MAKE_DIRS)

$(MAKE_DIRS):
    $(MAKE) -C $@ $(TARGET_INFO)

Now this works fine when I call the targets independently:

make apps; make clean_apps

However if I call them on the same commandline with:

make clean_apps apps

Then the apps target justs say nothing to do. I guess it's something to do with the dependency on the directories not having changed between invocations, but I thought the .PHONY command would avoid that problem...

I'm happy to know if there's a better way to deal with this.

Thanks, bob

user3677615
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  • This cannot "work fine" as written, since there is a typo in it (`clean_aps`). We can't help you if you don't show us the real makefile. – Beta May 27 '14 at 17:22

1 Answers1

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It is something much more simpler :

SUBDIRS :=  $(dir $(shell find apps -name "Makefile"))

.PHONY: all clean

all clean:
    $(foreach DIR, $(SUBDIRS), $(MAKE) $(MAKEFLAGS) -C $(DIR) $@;)
Chnossos
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