Store std_logic bits in ascending order into a large array

Question

I have an array of 2048-bits and i would want to store the incoming bits from 0 - 2047 in ascending bit order as it comes in FPGA on each rising edge of the clock cycle.

Eg:

array[0] <= 1st bit
array[1] <= 2nd bit
...
..
array[2047] <= 2048 th bit.

i know it can be done in VHDL by array indexing like

array(index) <= incoming_bit.

However, is there any other better approach like using bitwise operations (shifting) to achieve this. (without array indexing method), so that it eventually reduces the routing complexity in the FPGA.

Bruno JJE · Accepted Answer · 2014-01-05T10:57:49.830

Block RAM

The most efficient way to overcome routing problem in the case you describe is probably to store the bit in a block ram.

If you use the array you describe with a code written in the correct way, it is probably already what the synthesizer has infered for you.

But if you have used a reset in your code to load your array with all '0', the synthesizer won't be able to infer a BlockRAM, thus producing something that will probably not be as efficient.

FIFO

If you always use the bits one after the other, and don't use it after that, you can use a FIFO (that will probably be implemented with a BlockRAM by the synthesizer).

The bits will be stored in the FIFO as they come in, and only the oldest not yet processed bit will be presented to you at the output of the FIFO.

If the position of the bit matters, you can have a 11 bits counter that increment each time you read a bit from the fifo, thus it will always reflect the position of the bit you are fetching out of the FIFO.

Hope this helps.

i have never used a fifo in xilinx, in the core gen fifo configuration if i select Write width as 1, does it mean 1-bit data i.e each bit will have its own address.. am i right — powernest, Jan 05 '14 at 12:48
In your case, you chose an input and output width of 1. But there is no addresses for FIFO. New incomming bit are written in the FIFO, and you only have access to one bit at a time (first bit received will be the first bit accessible at the output, thus the First-In First-Out name). — Bruno JJE, Jan 05 '14 at 12:59

Morgan · Answer 2 · 2014-01-06T07:56:42.413

1

Barrel Shifter

If access to data is not required until loading 2048 is complete then in verilog you can imply a barrel shifter. Every clock cycle the data gets shifted down 1 position. At the end of the 2048 bits every thing would be in the correct place.

reg [2048-1:0] arr;

always @( posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    arr <= 'b0;
  end
  else begin
    arr[2048-1:0] <= {data_in, arr[2048-1:1]} 
  end
end

RAM

If access to first bits are required before the full 2048 bits have been loaded a RAM is ideal for this. RAMs typically can not be initialised in 1 clockcycle, no async reset. Therefore you must only read data from locations you have written to. You can specify initial conditions for an FPGA and I believe the FPGA startup routing can initialise it for you. but no easy way to clear it once running.

input            data_in;
input [10:0]     wr_addr;
reg   [2048-1:0] arr;

always @( posedge clk ) begin
  arr[wr_addr] <= data_in; 
end

// Optional FPGA initialisation
integer i;
initial begin
  for(i=0; i<2048; i=i+1) begin
    arr[i] <= 'b0;
  end
end

edited Jan 06 '14 at 07:56

answered Jan 03 '14 at 13:43

Morgan

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it would not be possible to wait for 2048 clock cycles, as these bits are used for some other computations parallely. so the bits should be in its correct position at all times. – powernest Jan 03 '14 at 14:15
1

The answer will always present the latest 2048 bit in ascending order in the array after the initial 2048 cycles for first filling of the array. Please elaborate on the problem for how you expect to get the initial 2048 bits if it is not possible to wait initially for 2048 cycles ? – Morten Zilmer Jan 03 '14 at 14:21
its basically like a pipelined process, the moment i get the bit in the 1st position, another process uses this bit and performs some computations. By the time it completes its computation , there could be a possiblity of 2 or more bits getting stuffed into the array. So the bit position is quite important. like 1st cycle [------0], 2nd[-----10], 3rd cycle[------110] so on and so forth. – powernest Jan 03 '14 at 15:39
@powernest: Does this mean that you don't actually need all 2048 bits at the same time but only the last few? Or would you then use the ones from the previous (transmission) cycle? – mbschenkel Jan 04 '14 at 23:52
Yes i would not need all 2048 bits at the same time, but as i mentioned earlier the bit position is quite vital. the bit stream should happen as [------0],[-----10],[-------010],[----1010]..so on. The bit should get appended from 0-to2047 in that order. – powernest Jan 05 '14 at 09:36
@powernest how many bits would you need? no point creating hardware to store them if not required. Will they be accessed randomly or always in sequence. A fifo structure might do if they are accessed once in order. – Morgan Jan 05 '14 at 09:51
@powernest I have corrected the order, and added a note on using a RAM . Can you update your question with the extra info provided so the comments can be removed, thanks. – Morgan Jan 06 '14 at 07:58

score 0 · Answer 3 · answered Jan 06 '14 at 21:50

Fundamentally, if you need access to all the bits at once, there's not much you can do about the routing complexity - the inputs and outputs all have to be there all the time.

If (on the other hand) you are getting the input bits one at a time (or only need access to them one at a time), then you could store them in a memory block which will reduce the resource usage.

Store std_logic bits in ascending order into a large array

3 Answers3

Barrel Shifter

RAM