How do you feed a file into memory made from custom modules (no reg) like with readmemb?

Question

For example, instead of using reg [3:0] RAM [0:31]; I've made my own module attempting to use using a hardwired FlipFlopMod.

This is what I'm trying to do (but you'll see it obviously doesn't work):

module mem_mod(addr, mem_out);
   input [4:0] addr;        // 5-bit addr bus
   output [3:0] mem_out;    // 4-bit inst/data out

   // a real flip flop instead of using reg.
   FlipFlopMod_4bit RAM [0:31] (1/*enabled*/, 4'b1111, q, nq);    // # of nibbles

   assign mem_out = RAM[addr]; // change this to an AND selector.

   // read binary code into RAM, prepare inst.txt 1st
   initial $readmemb("inst.txt", RAM);
endmodule

// Gated Flip Flop
module FlipFlopMod_1bit(clk, d, q, nq);
    input clk, d;
    output q, nq;

    wire and0, and1, d_inv;

    not(d_inv, d); // d and d_inv are someties referred to as R and S, respectively.

    // these two and gates cause the input to be latched only when clk
    // (enable) is high.
    and(and0, d, clk);
    and(and1, clk, d_inv);

    // These nor gates are the actual flipflop/latch.
    nor(nq, and0, q);
    nor(q, nq, and1);
endmodule

// 4 bit gated flip flop made using 1 bit gated flip flops.
module FlipFlopMod_4bit(clk, d, q, nq);
    input clk;
    input [3:0] d;
    output [3:0] q, nq;

    FlipFlopMod_1bit latch3 (clk, d[3], q[3], nq[3]);
    FlipFlopMod_1bit latch2 (clk, d[2], q[2], nq[2]);
    FlipFlopMod_1bit latch1 (clk, d[1], q[1], nq[1]);
    FlipFlopMod_1bit latch0 (clk, d[0], q[0], nq[0]);
endmodule

This is where I started from, using reg (this works):

module mem_mod(addr, mem_out);
   input [4:0] addr;        // 5-bit addr bus
   output [3:0] mem_out;    // 4-bit inst/data out

   reg [3:0] RAM [0:31];    // # of nibbles

   assign mem_out = RAM[addr];

   // read binary code into RAM, prepare inst.txt 1st
   initial $readmemb("inst.txt", RAM);
endmodule

As you can see, I'm not quite sure how to read each 4bit piece of data from a file into my custom array of FlipFlops, so that each of my FlipFlops holds a different value, like the reg example. I think I could probably just hard code 32 flip flops, and hard code the values in each parameter instead of reading the file, but that's no fun!

The file that I'm reading from (inst.txt) looks like this:

0001
0011
1000
0011
...
...
... etc, 32 lines total.

score 1 · Accepted Answer · answered May 27 '13 at 16:29

1

Are you trying to do this for synthesis or simulation? One easy hack is to use $fscanf and have some initialization code that iterates through a file copying one line from the file into your various flops. Of course for synthesis this won't work. Can I ask why you don't want to just use reg?

answered May 27 '13 at 16:29

Doov

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What's the difference between synthesis and simulation? I'd like to implement everything using only the most basic components (e.g. and, or, nand, etc). Could you provide a fscanf example like the one you described? – trusktr May 27 '13 at 20:15
1

Verilog (and other HDLs) provide you with the ability to write code that is non-synthesiable. This code isn't synthesized into hardware -- it's used solely for simulating (e.g. testing your synthesized code). Generally speaking for every module of verilog you write you should write a second module, which tests the first module. In the test bench module you can use code which isn't synthesized to gates in order to facilitate testing your module. – Doov May 28 '13 at 04:08
With regards to your desire to use "only the most basic components" I'd be remiss to point out that this is likely misguided. First of all the synthesis tools are going to take your code and synthesize it how they see fit for the given underlying hardware. It's not as though by instantiating an and gate you're actually going to get an and gate (at least not on an fpga or cpld). The underlying fpga fabric is made up of lookup tables, which create logical functions, but you're not actually getting some cmos gate of your desire (unless this is for an asic). – Doov May 28 '13 at 04:10
That stated you should probably stick to the reg...you're more likely to not get errors and you allow the synthesis tools do "do as they please" which is to say that you'll be able to go from fpga to fpga and keep the same HDL. In any event here's an example of using $fscanf to initialize something: – Doov May 28 '13 at 04:12
`integer file, i,j; reg [15:0] my_reg; initial begin file = $fopen("../some_file_path/file.txt", "r"); for(i = 0; i < some_val; i++) begin $fscanf(file, "%d\n", my_reg); mem[i] = my_reg; end $fclose(file); end` – Doov May 28 '13 at 04:14
Having some trouble figuring out how to format properly in the comment, but the basic idea is that you can read a value from a text file into a register and then do whatever you want with that register. Note that this is **not** synthesiable code and only used for simulation. I used this for doing some bizarre loading of data into a simulated off-chip sram. For certain cases it can be easier than using $writememh – Doov May 28 '13 at 04:19

How do you feed a file into memory made from custom modules (no reg) like with readmemb?

1 Answers1