Counter With Frequency divider is not incrementing

Question

The following code is written for an asynchronous counter. The program compiles fine but the counter value doesn't increment after 1. What am I doing wrong?

Here is the code:

//TOP

module CounterWithDivider(clk,reset,temp,q);

input clk,reset;
output [3:0]q;
output reg [3:0]temp;

reg [3:0]clkDivider;

TFF a(clkDivider,clk,reset,q[0]);
TFF b(clkDivider,q[0],reset,q[1]);
TFF c(clkDivider,q[1],reset,q[2]);
TFF d(clkDivider,q[2],reset,q[3]);

always @(posedge clk or negedge reset)
begin

if(~reset || clkDivider==12)
  clkDivider<=0;

else

if(clk)
begin

 clkDivider<=clkDivider+1;
 temp<=clkDivider;

end

end

endmodule

// T flip flop

module TFF(clkDivider,clk,reset,q);

input clk,reset;
input [3:0]clkDivider;
output reg q;

always @(posedge clk or negedge reset)
begin

if(~reset)
  q<=0;

else

if(clkDivider==11)
  q<=1;


end

endmodule

score 2 · Answer 1 · answered Mar 03 '13 at 17:37

2

A T-FlipFlop, or toggle flop should toggle its output when enabled, you just have:

if(clkDivider==11)
  q<=1;

Replace q<=1 with q<=~q to make it toggle when enabled.

answered Mar 03 '13 at 17:37

Morgan

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score 0 · Answer 2 · answered Mar 03 '13 at 18:49

As you mentioned, this is an asynchrous counter. The reason your Verilog simulation is not doing what you want is that TFF instance b is trying to sample its data input (clkDivider) using a different clock signal. clkDivider is clocked by signal clk, but you are trying to sample it using a different clock signal (q[0]).

You need to either find a way to synchronize the clkDivider signal into each of the other 3 clock domains, or use a fully synchronous design.

Counter With Frequency divider is not incrementing

2 Answers2