Do memory channels use separate pins for data bus in Intel i7-4600U?

Question

i7-4600U datasheet says that SA_DQ[63:0] is used for memory channel A. And SB_DQ[63:0] is used for memory channel B. So my understanding is that memory channel A and memory channel B use different processor pins for each own's data bus.

Is my understanding correct?

Answer 1

The presence of the of SA_DQ[63:0] and SB_DQ[63:0] pretty much says it all. The are two physical channels.

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If you still need a secondary "prof", you can also check the math of this statement in the datasheet

Theoretical maximum memory bandwidth of:
      — 21.3 GB/s in dual-channel mode assuming 1333 MT/s
      — 25.6 GB/s in dual-channel mode assuming 1600 MT/s

With 1333MT/s¹ and 8 Bytes per transfer we got 1333 * 8 = 10.664 GB/s.
In order to have a 21.3 GB/s peak, two channels must be used simultaneously, thus they must have separate pins.

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¹ Note that Mega-transfers per second is given by the internally multiplied bus clock (multiplier is fixed to four) times two, due to the double data rate. So 1333MT/s uses a 1333/2 = 666.67 MHz internal clock that corresponds to a 666.67/4 = 133.37 MHz bus clock.